Taking advantage of LVDS input buffers to implement sigma-delta A/D converters in FPGAs

This paper describes the implementation of a sigma-delta (/spl Sigma//spl Delta/) A/D converter within an FPGA, with minimal use of external analog components. The approach takes advantage of existing low-voltage differential signalling (LVDS) I/O pads; this allows the implementation of low-cost ADCs into existent FPGAs, even though such digital devices do not possess analog interfacing capabilities at first. The converter was implemented in an actual FPGA and had its performance evaluated.