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Efficient Timed Reachability Analysis Using Clock Difference Diagrams

1999159 citationsBook Chapter

Authors

Gerd Behrmann · Aalborg University

Kim G. Larsen · Aalborg University

Justin Pearson · Uppsala University

Carsten Weise · Aalborg University

Wang Yi · Uppsala University

Topics & Keywords

Formal Methods in Verification Embedded Systems Design Techniques VLSI and Analog Circuit Testing

UN Sustainable Development Goals

Industry, innovation and infrastructure

Publication Details

Published in: Lecture notes in computer science

DOI: 10.1007/3-540-48683-6_30

Field-Weighted Citation Impact: 16.13

Efficient Timed Reachability Analysis Using Clock Difference Diagrams | Researchclopedia