BEOL process integration with Cu/SiCOH (k=2.8) low-k interconnects at 65 nm groundrules

This paper describes a comprehensive characterization of a 65 nm, 300 mm wafer size interconnect technology with SiCOH material (k=2.8). Excellent film properties of the SiCOH material and precise process optimization enable the minimization of layer damage during etching and strip processes. 3D modeling reveals that the k-value of the SiCOH material was maintained at its initial value after the integration. Electrical yield, reliability and chip-to-package (CPI) evaluation are also presented. The results were comparable with the conventional SiCOH integration scheme.