Upset-tolerant CMOS SRAM using current monitoring: prototype and test experiments

200229 citationsPreprint

Authors

T. Calin · Techniques of Informatics and Microelectronics for Integrated Systems Architecture

Fabian Vargas · Techniques of Informatics and Microelectronics for Integrated Systems Architecture

M. Nicolaidis · Techniques of Informatics and Microelectronics for Integrated Systems Architecture

Abstract

This paper presents implementation and test experiments of a current monitoring technique for on-line detection and correction of transient faults in CMOS static RAMs. This technique combines built-in current sensing (BICS) with parity code to achieve zero detection latency and single-bit error correction.

Topics & Keywords

Radiation Effects in Electronics VLSI and Analog Circuit Testing Low-power high-performance VLSI design

Publication Details

DOI: 10.1109/test.1995.529816

Field-Weighted Citation Impact: 2.74

Command Palette

Upset-tolerant CMOS SRAM using current monitoring: prototype and test experiments

Authors

Abstract

Topics & Keywords

Publication Details