A VLSI module for IEEE floating-point multiplication/division/square root

The major objective of this VLSI module design is to determine how to modify a fast floating-point multiplier so that it can perform division and square root in accordance with IEEE standards. This has been achieved by applying the Newton-Ralphson iteration only on the mantissa and adjusting the iterated result by a rounding algorithm. Using 1.0- mu m CMOS standard cell technology, the total area of this module is approximately 7.0 mm*6.5 mm, which is just 25% larger than the floating-point multiplier. The module can compute multiplication, division, and square root in 3, 31, and 43 cycles, respectively. The cycle time, under nominal conditions, is expected to be 20 ns.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>