The CHI, a new Fastbus interface and processor

The CERN Host Interface (CHI) is a family of interfaces to interconnect Fastbus, VMEbus, and external host computers. The Fastbus interface consists of a processor board (CHI-P) and host-specific I/O ports allowing connection using fast parallel or serial interfaces. For efficiency in a data acquisition chain, the CHI-P contains a 1-MB triple-port memory which allows concurrent access by Fastbus (as master or slave), the host link, and the 4.5 MIPS onboard processor. The processor, an MC68030 with floating point coprocessor, also has 1 Mb of local memory and 1.25 Mb of EPROM (electrically programmable ROM). The hardware modularity allows the CHI-P to be used as an interface, general-purpose Fastbus test module, or an embedded Fastbus processor. The resident software supports its use in each of these modes. Remote procedure calls, an ISO-style transport service, and the Standard Routines for Fastbus are provided on the host and on the CHI-P, allowing the migration of software between the two. Menu-driven test software and an interactive interpreted/compiled language support its use in a test environment.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>