Low noise electronics for the CLEO III silicon detector

We report here the status of the CLEO III silicon vertex detector electronics. The CLEO III silicon detector is a 4-layer barrel-style device which spans 93% of the solid angle observing the interaction region. All layers will be constructed with double-sided silicon. The innermost layer must be able to handle large singles rates associated with a detector situated near the interaction region. In order to cover the required solid angle, the outermost layer is 55 cm long and presents a large capacitive load to the front-end electronics. The electronics chain chosen to meet this challenge consists of a low noise cascode preamplifier followed by an ADC on each channel. The system issues will be described herein together with the chosen solutions, noise performance of each subsystem prototype, and expected results of the full system.