Multiplierless fast Fourier transform architecture

A multiplierless processor architecture is proposed for hardware implementation of fast Fourier transform. Distributed arithmetic is applied to simplify expensive butterfly operations and twiddle multiplications. The novel architecture can largely reduce area cost by replacing complex multipliers and adders with DA lookup tables. Both 8-bit and 16-bit 64-point FFT processors were designed, and the synthesis result shows the designs can attain much lower area cost while keeping real-time processing speed.