A Network Tearing Technique for FPGA-Based Real-Time Simulation of Power Converters

The realm of hardware-in-the-loop simulation resorts to field-programmable gate arrays to achieve time steps below 1 $\mu\hbox{s} $. Such low time steps are of importance for the aerospace and automotive industries, where power converters have their switching frequencies in the 10- to 200-kHz range. This paper proposes a network tearing technique that allows subsets of switches to be treated independently, alleviates embedded memory requirements, and reduces the computational burden. An iterative algorithm is used to determine the state of naturally commutated switches, thus offering a realistic model of the power converter, independently of its operation mode or topology. A Gauss-Jordan processing unit is implemented to solve interface voltages/currents from the torn circuit. Custom floating-point operators are used to ensure good accuracy, high-frequency operation, and low computational latency. A neutral-point-clamped converter case study is presented to demonstrate the effectiveness of the method. Simulation results are validated against a reference model at a 750-ns time step and a 30-kHz sine pulsewidth modulation switching frequency.