Design of ADC in 25 μm pixels pitch dedicated for IRFPA image processing at LETI

LETI has been involved in IRFPA development since 1978, the design department (LETI/DCIS) has focused its work on new ROIC architecture since many years. The trend is to integrate advanced functions into the CMOS design in the aim of making cost efficient sensors. The purpose of this paper is to present the latest developments of an Analog to Digital Converter embedded in a 25&#956;m pixel. The design is driven by several goals. It targets both long integration time and snapshot exposure, 100% of image frame time being available for integration. All pixels are integrating the IR signal at the same time. The IR signal is converted into digital by using a charge packet counter. High density 130nm CMOS allows to use many digital functions such as counting, memory and addressing. This new structure has been applied to 25&#956;m pitch bolometer sensors with a dedicated 320 x 240 IRCMOS circuit. Due to smart image processing in the CMOS, the bolometer architecture requirements may become very simple and low cost. The room temperature sensitivity and the DC offset are solved directly in the pixel. This FPA targets low NETD (<50mK), a variation of 80 Kelvin for the FPA temperature, 14 bits output at 50/60Hz video rate.