A Two's Complement Parallel Array Multiplication Algorithm

1973643 citationsJournal Article

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Abstract

An algorithm for high-speed, two's complement, m-bit by n-bit parallel array multiplication is described. The two's complement multiplication is converted to an equivalent parallel array addition problem in which each partial product bit is the AND of a multiplier bit and a multiplicand bit, and the signs of all the partial product bits are positive.

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Interconnection Networks and Systems Cellular Automata and Applications Engineering and Test Systems

Publication Details

Published in: IEEE Transactions on Computers

Volume C-22, Issue 12, pp. 1045-1047

DOI: 10.1109/t-c.1973.223648

Field-Weighted Citation Impact: 5.35

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A Two's Complement Parallel Array Multiplication Algorithm

Authors

Abstract

Topics & Keywords

Publication Details