Upset hardened memory design for submicron CMOS technology

19961,131 citationsJournal Article

Authors

T. Calin · Techniques of Informatics and Microelectronics for Integrated Systems Architecture

M. Nicolaidis · Techniques of Informatics and Microelectronics for Integrated Systems Architecture

Raoul Velazco · Techniques of Informatics and Microelectronics for Integrated Systems Architecture

Abstract

A novel design technique is proposed for storage elements which are insensitive to radiation-induced single-event upsets. This technique is suitable for implementation in high density ASICs and static RAMs using submicron CMOS technology.

Topics & Keywords

Radiation Effects in Electronics VLSI and Analog Circuit Testing Integrated Circuits and Semiconductor Failure Analysis

UN Sustainable Development Goals

Affordable and clean energy

Publication Details

Published in: IEEE Transactions on Nuclear Science

Volume 43, Issue 6, pp. 2874-2878

DOI: 10.1109/23.556880

Field-Weighted Citation Impact: 2.74