Simultaneous double side grinding of silicon wafers: a mathematical study on grinding marks

Most Integrated Circuits (ICs) are built on silicon wafers. A series of processes are required to manufacture high quality silicon wafers. Simultaneous Double Side Grinding (SDSG) is one of the processes used to flatten wire-sawn wafers. A critical issue in SDSG is the grinding marks on wafer surfaces. Several mathematical models have been proposed to predict the grinding marks in Single Side Grinding (SSG). However, no papers have ever been published to systematically study the grinding marks in SDSG. This paper first gives a brief literature review on mathematical models for grinding marks in SSG of silicon wafers. It then presents the development of a mathematical model for grinding marks in SDSG of silicon wafers. This developed model is then used to study the effects of SDSG parameters on the curvature of the grinding marks and the distance between adjacent grinding marks. Finally this paper discusses one practical application of the model.