A Multimode Transmitter in 0.13 $\mu\hbox{m}$ CMOS Using Direct-Digital RF Modulator

This paper presents a system-independent transmitter architecture based on a direct-digital RF-modulator which combines the D/A conversion, up-conversion, unwanted sideband rejection, power control, and part of the digital image-rejection filtering into a single mixed-signal circuit block. The multimode capability of the architecture is demonstrated with WCDMA, EDGE, and WLAN system requirements. The modulator achieves 90 dB of power control range and with an external power amplifier module, WCDMA EVM of less than 2% from signal powers of -20 dBm to +25 dBm. The noise floor level defined by the quantization noise at 190 MHz offset from the carrier is -150 dBc/Hz measured at the output of the PA with +25 dBm signal power. The analog power consumption with the maximum signal power level is 92 mW and scales down to 46 mW when reducing the signal level to -43 dBFS. The digital power consumption is 65 mW. The chip is implemented with a standard 0.13 mum 1.2 V digital CMOS with total silicon area of 4 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .