A MOS four-quadrant analog multiplier using the quarter-square technique

1987131 citationsJournal Article

Authors

J.S. Pena-Finol · Centre for Research and Development in Telecommunications (Brazil)

J.A. Connelly · Georgia Institute of Technology

Abstract

A circuit configuration for a four-quadrant analog multiplier in MOS integrated circuit technology is described. It is based on the quarter-square algebraic identity and uses differential summer and differential squaring stages. The multiplier achieves a linearity of 0.44%, a -3-dB bandwidth of 5 MHz, a dynamic range of 87 dB, and a total harmonic distortion of 0.59%. The circuit was fabricated in a 5-/spl mu/m double-polysilicon p-well CMOS process. Typical power consumption is 10 mW. Chip size is 500 mil/SUP 2/.

Topics & Keywords

Analog and Mixed-Signal Circuit Design Low-power high-performance VLSI design Advancements in PLL and VCO Technologies

UN Sustainable Development Goals

Affordable and clean energy

Publication Details

Published in: IEEE Journal of Solid-State Circuits

Volume 22, Issue 6, pp. 1064-1073

DOI: 10.1109/jssc.1987.1052856

Field-Weighted Citation Impact: 2.56