Thermal Select MRAM with a 2-bit Cell Capability for beyond 65 nm Technology Node

We report on a novel thermal select (TS) MRAM with multilevel programming capability. Exchange bias pinning of a magnetic free layer (FL) was used to achieve a thermally stable bit and to reduce writing currents. This report shows experimental data for a TS-based magnetic tunnel junction (MTJ) with a size of 50 times90 nm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , the smallest size reported so far. Multilevel capability with 2 bits per 1-transistor and 1-MTJ (1T1MTJ) is also demonstrated on a 70 times 140 nm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> MTJ. With the advanced 2-bit cell concept, a 70% increase in effective bit density can be achieved at 65 nm technology node