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The LHCb experiment is currently being installed at the Large Hadron Collider at CERN (Geneva, Switzerland). In order to reduce the amount of data storage for offline analysis, a trigger system is required. The Level-0 Decision Unit (LODU) is the central part of the first trigger level. It is a full custom 16 layers board using advanced FPGAs in BGA package. The LODU receives information from the Level-0 sub-triggers (432 bits @ 80 MHz) which transmit the data via high speed optical links running at 1.6 Gb/s. The processing is implemented using a 40 MHz synchronous pipelined architecture. It performs a simple physical algorithm to compute at 40 MHz the Level-0 trigger decision in order to reduce the data flow down to 1 MHz for the next trigger level. The internal design of the processing FPGA is mainly composed by a Partial Data Processing (PDP) and a Trigger Definition Unit (TDU). The aim of the PDP is to adjust the clock phase, perform the time alignment, prepare the data for the TDU and monitor the data processing. The TDU is flexible and allows to fully re-configure all the trigger conditions without any re-programming the FPGAs through the Experiment Control System (ECS).