Area-time efficient modulo 2/sup n/-1 adder design

199463 citationsJournal Article

Authors

C. Efstathiou · Hellenic Telecommunications Organization (Greece)

John Kalamatianos · University of Patras

Abstract

In this paper the design of modulo 2/sup n/-1 adders is discussed. Two new design procedures are given, based on the one-level and the two-level carry look-ahead addition algorithms. The adders designed according to the procedures proposed in this paper are significantly more efficient, with respect to speed and the cost function area-time product, than the corresponding adders already known from open literature.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>

Topics & Keywords

Low-power high-performance VLSI design Parallel Computing and Optimization Techniques Analog and Mixed-Signal Circuit Design

Publication Details

Published in: IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing

Volume 41, Issue 7, pp. 463-467

DOI: 10.1109/82.298378

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Area-time efficient modulo 2/sup n/-1 adder design

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Publication Details