A Sub-1-V 65-nm MOS Threshold Monitoring-Based Voltage Reference

This brief presents a sub-1-V 65-nm MOS threshold voltage monitoring-based voltage reference (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> sensor) with current-mode second-order temperature compensation. By utilizing the different temperature properties of P+ diffusion and poly resistors, auxiliary nonlinear temperature compensation is implemented in the Brokaw MOS V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> circuit. By doing so, it attenuates the nonlinear temperature effect of gate-to-source voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> ), thus lowering the temperature coefficient (T.C.). Fabricated in a UMC 65-nm CMOS process, the results show that the circuit can generate an average reference voltage of 474 mV. This is close to the extrapolated V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> for a low-threshold nMOS transistor at absolute zero temperature. In a range from -40 °C to 90 °C, the best T.C. achieved by the circuit is 24.5 ppm/°C and the average T.C. over 15 samples is 40 ppm/°C.