Floating point datapath synthesis for FPGAs

Floating point arithmetic is used extensively in many applications across multiple market segments. While high performance IEEE754 floating point cores are available for FPGAs, a large datapath consisting of multiple cores is resource intensive, with often poor system performance. This paper will introduce a new approach to floating point datapath design for FPGAs, using fused datapath synthesis. The result is a more balanced, high performance implementation, typically saving 50% in both logic resources and latency. Using Stratix reg 3SE260 devices, 50 GFLOPs double precision and 125 GFLOPs single precision can be realized.