A digital CMOS design technique for SEU hardening

2000121 citationsJournal Article

Authors

S. Büchner · Schiller International University

Dale McMorrow · United States Naval Research Laboratory

Abstract

A new cell design technique is described which may be used to create SEU hardened circuits. The technique uses actively biased, isolated well transistors to prevent transients in combinational logic from reaching the output node.

Topics & Keywords

Advancements in Semiconductor Devices and Circuit Design Low-power high-performance VLSI design Semiconductor materials and devices

UN Sustainable Development Goals

Affordable and clean energy

Publication Details

Published in: IEEE Transactions on Nuclear Science

Volume 47, Issue 6, pp. 2603-2608

DOI: 10.1109/23.903815

Field-Weighted Citation Impact: 2.70