Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density

In this papel; we investigate the speed and area-eficiency of FPGAs employing “logic clusters ” containing multiple LUTs and registers as their logic block. We introduce a new, timing-driven tool (T-VPack) to “pack ” LUTs and registers into these logic clusters, and we show that this algorithm is superior to an existing packing algorithm. Then, using a realistic routing architecture and sophisticated delay and area models, we empirically evaluate FPGAs composed of clusters ranging in size from one to twenty LUTs, and show that clusters of size seven through ten provide the best area-delay trade-o @ Compared to circuits implemented in an FPGA composed of size one clusters, circuits implemented in an FPGA with size seven clusters have 30 % less delay (a 43 % increase in speed) and require 8 % less area, and circuits implemented in an FPGA with size ten clusters have 34 % less delay (a 52 % increase in speed), and require no additional area. 1.