Parasitic extraction: current state of the art and future trends

With the increase in circuit performance (higher speeds) and density (smaller feature size) in deep submicron (DSM) designs, interconnect parasitic effects are increasingly becoming more important. This paper first surveys the state of the art in parasitic extraction for resistance, capacitance and inductance. The paper then covers other related topics such as interconnect modeling, delay calculation and signal integrity issues such as crosstalk. Finally, some future trends and issues related to parasitic extraction and interconnect modeling are presented.