An Efficient BICS Design for SEUs Detection and Correction in Semiconductor Memories

200574 citationsJournal Article

Authors

B. Gill · Case Western Reserve University

M. Nicolaidis · Techniques of Informatics and Microelectronics for Integrated Systems Architecture

Francis Wolff · Case Western Reserve University

C. Papachristou · Case Western Reserve University

S.L. Garverick · Case Western Reserve University

Abstract

We propose a new built-in current sensor (BICS) to detect single event upsets (SEUs) in SRAM. The BICS is designed and validated for 100 nm process technology. The BICS reliability analysis is provided for process, voltage and temperature variations, and power supply noise. The BICS detects various shapes of current pulses generated due to particle strike. The BICS power consumption and area overhead are also provided. The BICS is found to be very reliable for process, voltage and temperature variations and under stringent noise conditions.

Topics & Keywords

Radiation Effects in Electronics Integrated Circuits and Semiconductor Failure Analysis VLSI and Analog Circuit Testing

UN Sustainable Development Goals

Affordable and clean energy

Publication Details

Published in: Design, Automation, and Test in Europe

DOI: 10.1109/date.2005.54

Field-Weighted Citation Impact: 9.58