A 10-bit 60-MS/s Low-Power Pipelined ADC With Split-Capacitor CDS Technique

In this brief, a split-capacitor correlated double sampling (SC-CDS) technique is proposed to improve the performance of CDS. Using the proposed technique, low-gain operational amplifiers (op-amps) can be employed to implement a low-power pipelined analog-to-digital converter (ADC). A power-efficient class-AB pseudodifferential op-amp and its corresponding integrator-based common-mode stabilization (IB-CMS) method are developed to further reduce the power consumption of the ADC. The proposed pipelined ADC fabricated in a pure digital 0.18-¿m 1P5M CMOS process consumes 18 mW at 60 MS/s from a 1.8-V power supply. The active die area is 0.84 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .