Symbolic layout compaction under conditional design rules

199211 citationsJournal Article

Authors

Chung‐Kuan Cheng · University of California, San Diego

S.-Z. Yao · University of California, San Diego

Abstract

The compaction of IC layouts subjected to conditional spacing rules in multiple-level metal technology is addressed. The constraints imposed by conditional rules make the automatic compaction of layout much more difficult than when the usual minimum separation rules are applied. To solve the problem, each conditional spacing rule is formulated with a set of arcs in the constraint graph representation. It is proven that finding the optimal solution under one bridge rule is NP-complete. A graph-theory method of compaction which, by reducing the problem size, can efficiently obtain an optimal solution is proposed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>

Topics & Keywords

VLSI and FPGA Design Techniques Advancements in Photolithography Techniques VLSI and Analog Circuit Testing

Publication Details

Published in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volume 11, Issue 4, pp. 475-486

DOI: 10.1109/43.125095

Field-Weighted Citation Impact: 0.52

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Symbolic layout compaction under conditional design rules

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Abstract

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Publication Details