Optimum buffer circuits for driving long uniform lines

The design of optimum buffer circuits for driving long uniform lines is discussed. Given a uniform line, the size of the buffer driving the line, and the value of the capacitive load driven by the line, the problem considered consists of determining the type, number, and position of buffers that minimize the delay in the line. A variation of this problem that is also considered consists of minimizing the delay in the line when the area occupied by the buffers is constrained; this leads to the solution of the problem of minimizing the delay in driving a pure capacitive load under buffer area constraint. The optimal solution is formally developed, and some very good approximate solutions that can be obtained via simple computations are presented. It is shown that accepting a small increase in delay (of usually 5% over the minimum) can lead to a significant (about 50%) decrease in the area occupied by the buffers. Design curves that allow the reader to determine the optimum buffers with little effort are presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>