Design and Characteristics of an Integrated Multichannel Ramp ADC Using Digital DLL Techniques for Small Animal PET Imaging

This paper presents a novel design of an integrated 12-bit multi-channel single-slope ramp analog-to-digital converter (ADC) for a small animal positron emission tomography(PET) imaging system. The proposed ADC is a part of a monolithic front-end readout application-specific integrated circuit(ASIC) which is dedicated to the detector modules consisting of LYSO scintillation crystals read out on both sides by the multi-channel plate (MCP) photodetectors. The function of the ADC is to digitize the voltage signals from a large number of readout channels. Digital delay-locked loop (DLL) techniques are proposed to realize time interpolations in order to reduce the conversion time and to enhance the resolution. Both high precision and low power are obtained. An eight-channel prototype chip is implemented in AMS 0.35 μm CMOS technology. The available resolution of the ADC is 9 ~ 12 bits. The maximum DNL and INL of the fine conversion in the ADC is ±0.75 LSB and ±0.5 LSB, respectively. The static power consumption of the ADC is 3 mW + 0.2 mW/Channel. This ADC architecture provides a possibility to integrate low-noise front-end readout circuits, time-to-digital converters and ADC together into a monolithic ASIC and to output both the energy quantity and the time information with digital representations for PET imaging systems.