Improved Ge Surface Passivation With Ultrathin $ \hbox{SiO}_{X}$ Enabling High-Mobility Surface Channel pMOSFETs Featuring a HfSiO/WN Gate Stack

To realize high-mobility surface channel pMOSFETs on Ge, a 1.6-nm-thick SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">X</sub> passivation layer between the bulk Ge substrate and HfSiO gate dielectric was introduced. This approach provides a simple alternative to epitaxial Si deposition followed by selective oxidation and leads to one of the highest peak hole mobilities reported for unstrained surface channel pMOSFETs on Ge: 332 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2 </sup> middotV <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> middots <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> at 0.05 MV/cm-a 2times enhancement over the universal Si/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> mobility. The devices show well-behaved output and transfer characteristics, an equivalent oxide thickness of 1.85 nm and an I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF </sub> ratio of 3times10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> without detectable fast transient charging. The high hole mobility of these devices is attributed to adequate passivation of the Ge surface