Combinational profiles of sequential benchmark circuits

A set of 31 digital sequential circuits described at the gate level is presented. These circuits extend the size and complexity of the ISCAS'85 set of combinational circuits and can serve as benchmarks for researchers interested in sequential test generation, scan-based test generation, and mixed sequential/scan-based test generation using partial scan techniques. Although all the benchmark circuits are sequential, synchronous, and use only D-type flip-flops, additional interior faults and asynchronous behavior can be introduced by substituting for some or all of the flip-flops their appropriate functional models. The standard functional model of the D flip-flop provides a reference point that is independent of the faults particular to the flip-flop implementation. A testability profile of the benchmarks in the full-scan-mode configuration is discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>