A low-cost, highly reliable SEU-tolerant SRAM: prototype and test results

199524 citationsJournal Article

Authors

T. Calin · Techniques of Informatics and Microelectronics for Integrated Systems Architecture

Fabian Vargas · Techniques of Informatics and Microelectronics for Integrated Systems Architecture

M. Nicolaidis · Techniques of Informatics and Microelectronics for Integrated Systems Architecture

Raoul Velazco · Techniques of Informatics and Microelectronics for Integrated Systems Architecture

Abstract

This paper presents the architecture of a CMOS static RAM which is tolerant to radiation-induced upsets. It employs transient current sensing circuits to achieve concurrent, event-driven SEU detection and correction. Tests with simulated upsets and preliminary radiation tests showed the detection of all upsets and proved the effectiveness of the approach.

Topics & Keywords

Radiation Effects in Electronics VLSI and Analog Circuit Testing Low-power high-performance VLSI design

Publication Details

Published in: IEEE Transactions on Nuclear Science

Volume 42, Issue 6, pp. 1592-1598

DOI: 10.1109/23.488754

Field-Weighted Citation Impact: 0.00

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A low-cost, highly reliable SEU-tolerant SRAM: prototype and test results

Authors

Abstract

Topics & Keywords

Publication Details