The leading edge of production wafer probe test technology

Microelectronic wafer and die level testing have undergone significant changes in the past few years. This work's first section describes today's leading edge characteristics for numerous areas of this test technology including the minimum I/O pad pitch, advances in contactor technologies, maximum number of l/Os probed, maximum number of die tested in parallel, the largest prober and substrates, and the maximum frequencies being tested at the wafer level. The second section discuss the leading edge practices in three critical areas of wafer test: probe contactor cleaning, I/O pad damage minimization, and sorting good from bad die. The final section present the communication methods between the design and the probe test organizations and some state-of-the-art examples for I/O pad designs.