Laboratory study of potential induced degradation of silicon photovoltaic modules

The standard system architecture of PV installations exposes solar modules to bias voltages of several hundred volts. Recently it became apparent that high bias voltages can have negative effects on the long-term performance of standard screen-printed crystalline silicon solar cells. This paper focuses on the study of this potential induced degradation effect (PID) under laboratory conditions. A corona-discharge assembly was used to polarize mini modules as well as a setup to expose 60-cell modules to high bias under wet conditions. Different encapsulation setups and cell process variations are studied to identify the necessary components leading to PID. I-V measurements, electroluminescence imaging and dark lock-in thermography are employed to obtain detailed characteristics of PID. A correlation between local current loss and shunt conductivity was found. Options to prevent PID on module and cell levels were found and verified experimentally.