Border Traps in MOS Devices

This paper mainly introduce the characteristic, properties and forming mechanism of border traps and their effects on MOS devices performance reported abroad. Two kinds of theoretical models for border traps and their possible microscopic natures are presented. It is shown that the effect are different for fast border traps and slow border traps. Two measuring techniques C-V test and DTBT for border traps are discussed. Finally, border traps annealing effects and their correlation with oxide traps and interface traps are demonstrated.