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This work proposes an energy-recycling (ER) technique for power management among a photovoltaic (PV) module, battery, and load in light energy harvesting systems. The ER technique delivers all harvested PV energy directly to the load with surplus energy recycled from the load to the battery, and can eliminate inductor-sharing power switches in single-inductor dual-input dual-output (SIDIDO) converters. Accordingly, the proposed dual-path 3-switch (2P3S) converter, which operates in discontinuous-conduction mode and regulates load voltage by constant-on-time pulse-skipping modulation, was developed. Under dynamic PV power P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P</sub> and load power P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</sub> profiles, the 2P3S converter's advantageous applications are identified by comparing efficiencies of state-of-the-art SIDIDO converters. The overall efficiency under static P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P</sub> and P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</sub> profiles and indirect-path efficiency under dynamic P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P</sub> and P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</sub> profiles are maximized by optimizing switch sizes and on-time. The chip has three power switches and a controller employing low-power circuits, and is fabricated in 0.5 μm CMOS process with 0.5 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> active area. The measured controller current is 0.85 μA. Under static P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P</sub> and P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</sub> profiles, for P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P</sub> of 40 μW, efficiency is 80.7% to 95.0% for 0 μW to 20 mW load power. Compared with other state-of-the-arts, the 2P3S converter has the highest efficiency under static P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P</sub> and P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</sub> profiles and higher efficiency with more PV energy directly consumed by the load under dynamic P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P</sub> and P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</sub> profiles.
Published in: IEEE Journal of Solid-State Circuits
Volume 51, Issue 11, pp. 2716-2728