Analysis of propagation-delays in high-speed bipolar gates

This paper presents novel accurate propagation-delay expressions for evaluating the speed performances of very-high-speed bipolar gates. Our expressions were derived by sensitivity analysis though SPICE simulations. We previously developed high-speed emitter-coupled logic (ECL) and source-coupled logic (SCL) gates for high-speed operations using transient currents in emitter or source followers. In this work, we analyze the propagation-delay times of the conventional and proposed bipolar ECL gates using novel propagation-delay expressions. The base-emitter diffusion capacitance (CD) is a speed-limiting parameter in a bipolar gate. The ECL gate mainly consists of the current switch and emitter followers. Thus, we distinguished the base-emitter diffusion capacitances in current switch transistors and emitter follower ones to enhance the accuracy of the expressions by sensitivity analysis. Our expressions for both conventional and novel high-speed ECL gates were expressed as the linear weighted sum of 11 time constants. The propagation-delay times in conventional and novel high-speed gates calculated from our expressions agree well with simulation results. The expressions show that our circuit technique can reduce the delay times for R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</sub> C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> and τ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">F</sub> in the current switch transistors, which are dominant speed limiting time constants in high-speed bipolar ECL gates.