Design of a $V$ -Band 20-dBm Wideband Power Amplifier Using Transformer-Based Radial Power Combining in 90-nm CMOS

This paper presents a V-band 1.2-V wideband power amplifier (PA) with a compact four-way radial power combiner in a 90-nm CMOS process. A transformer-based radial power combiner with a 1-dB insertion loss at 60 GHz and a 0.043-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> compact size is designed for high-output-power combining and wideband load-pull matching. This PA achieves the saturated output power (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SAT</sub> ) of 20.6 dBm, the maximum power-added efficiency (PAE <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> ) of 20.3%, and a 20.1-dB small-signal gain (S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">21</sub> ) at 60 GHz. The PA maintains a flat 20-dBm P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SAT</sub> with PAE <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> better than 17.3% within 50-64 GHz, and it has a 3-dB bandwidth (BW) of 24.5 GHz (41.8-66.3 GHz). The chip area without pads is 0.432 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . To the best of the author's knowledge, this V-band PA with a flat frequency response of 20-dBm P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SAT</sub> presents the widest large-signal BW (50-64 GHz) compared with the reported 60-GHz CMOS high-output PAs.