Analysis and Demonstration of an IIP3 Improvement Technique for Low-Power RF Low-Noise Amplifiers

This paper describes a linearization method to enhance the third-order distortion performance of a subthreshold common-source cascode low-noise amplifier (LNA) without extra power consumption by using passive components. An inductor between the gate of the cascode transistor and the power supply in combination with a digitally programmable capacitor between the gate and the drain of the cascode transistor enable to improve the third-order intermodulation intercept point (IIP3) of a subthreshold LNA. The theoretical mechanisms that underlie the linearity improvement are analyzed comprehensively under the consideration of the LNA's input stage, cascode stage, reverse isolation, and stability. A 1.8-GHz LNA was designed and fabricated using 0.11-μm CMOS technology to prove the concept. Measurement results reveal that the linearized low-power LNA has a 14.8-dB voltage gain, a 3.7-dB noise figure, and a -3.7-dBm IIP3 with a power consumption of 0.336 mW.