Test and Debug Strategy for High Speed JESD204B Rx PHY

In this paper, we propose a test and debug methodology to support at-speed testing of the high-speed mixed signal JESD204B Receiver Physical Layer (JESD204B Rx PHY) serial interface in 28nm Silicon-On-Insulator (SOI) technology. A mixed signal Built-in-Self-Test (BIST) is implemented to target testing of both the 2.4GHz and 60MHz mixed signal domains of the PHY. The BIST consists of an analog pattern generator which injects 2.4Gbps JESD204B compliant differential serial data, an auto-clock phase rotation to stress Clock Data Recovery (CDR) block and a checker to validate the 60MHz parallel digital data received at the output of the PHY. A scan chain structure is added to provide additional coverage of stuck-at and 60MHz at-speed transition faults. To facilitate debugging, a second set of serial pattern generator and data checker is implemented at the digital boundary. The BIST provides a fault coverage of 78.68% and 81.67% for stuck-at and 2.4GHz domain at-speed transition faults respectively for the PHY digital logic, while an ATPG coverage of 99.22% and 94.13% is achieved for stuck-at and 60MHz at-speed transition faults respectively using the scan chain structure. The BIST area and current consumption overhead is seen to be 0.5% and 2.5% respectively, thus providing a low cost test solution.