Calculation of Printed Circuit Board Power-Loop Stray Inductance in GaN or High <italic>di/dt</italic> Applications

This paper is concerned with the determination of parasitic inductance values in very fast switching power devices. To keep improving today's power converters, new technologies are studied, which exhibit very low switching times. The wide-bandgap semiconductors are among the key aspects of these improvements. Thanks to their internal properties, they allow very fast <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">di/dt</i> and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dv/dt</i> with very small footprint. Stray loop inductance needs to be kept low, as it creates high peak voltage upon switching of a transistor with fast <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">di/dt</i> . In particular, the stray inductance value with respect to the loop size and geometry needs to be calculated accurately at the design stage of the power converters. This paper analyzes three loop geometries and studies one with minimized stray inductance and optimal current distribution. An analytical method is proposed, which uses the Biot-Savart law for an accurate analytical estimation of the magnetic field intensity in the selected geometry, leading to inductance calculation. A comparison between the classical two-plate inductance estimation formula and the proposed stray inductance estimation is presented, proving more accurate value with the method proposed in this paper. Finally, an experiment has validated the new inductance estimation formula.