Fan-Out Wafer-Level Packaging for Heterogeneous Integration

201884 citationsJournal Article

Authors

John H. Lau · ASM Pacific Technology (China)

Ming Li · ASM Pacific Technology (China)

Margie Li Qingqian · ASM Pacific Technology (China)

Tony Chen

Iris Xu

Qing Xiang Yong · Huawei Technologies (China)

Zhong Cheng · Huawei Technologies (China)

Nelson Fan

Abstract

The design, materials, process, fabrication, and reliability of a heterogeneous integration of four chips and four capacitors by a fan-out wafer-level packaging (FOWLP) method are investigated in this paper. Emphasis is placed on the application of a new assembly process for fabricating the redistribution layers of the FOWLP. Reliability assessments, such as the thermal cycling and drop test, are also performed.

Topics & Keywords

3D IC and TSV technologies Electronic Packaging and Soldering Technologies Electromagnetic Compatibility and Noise Suppression

Publication Details

Published in: IEEE Transactions on Components Packaging and Manufacturing Technology

Volume 8, Issue 9, pp. 1544-1560

DOI: 10.1109/tcpmt.2018.2848649

Field-Weighted Citation Impact: 5.74

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Fan-Out Wafer-Level Packaging for Heterogeneous Integration

Authors

Abstract

Topics & Keywords

Publication Details