A Low-Power ASIC Implementation of Multi-Core OpenSPARC T1 Processor on 90nm CMOS Process

In this paper, a hierarchy low-power design flow has been proposed. Low-power design techniques for digital ASIC design have been implemented with this proposed flow such as clock gating technique at RTL synthesis stage, multi-threshold voltage and power switching technique at back-end stage for power optimization. These low-power flow and techniques are implemented on an open source RTL of OpenSPARC T1 processor core. Firstly, the core is run synthesis and place-and-route without applying any low-power optimization techniques from front-end to back-end stage. Secondly, the core is completed by using the low-power design techniques. This work is implemented on open 90nm CMOS process with the EDA tools.