A V-Band Power Amplifier With 23.7-dBm Output Power, 22.1% PAE, and 29.7-dB Gain in 65-nm CMOS Technology

This article presents a V-band three-stage power amplifier (PA) fabricated in 65-nm CMOS technology with remarkable performances of output power, efficiency, and power gain. A cascode amplifier is proposed to optimize the power performances at millimeter-wave (mm-wave). A current-combining radial structure transformer power combiner with a low impedance transmission line is used to combine four differential power cells efficiently and to further improve the output power. Meanwhile, two common-source (CS) amplifiers are cascaded to achieve high power gain. The measured results of the proposed PA demonstrate the saturated output power ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\mathrm {sat}}$ </tex-math></inline-formula> ) of 23.7 dBm, output 1-dB compression point ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OP</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1 dB</sub> ) of 19.9 dBm, peak power added efficiency (PAE) of 22.1%, and 29.7-dB power gain at 60 GHz with only 0.653-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> chip size.