A Survey on Hardware Security Techniques Targeting Low-Power SoC Designs

In this work, we survey hardware-based security techniques applicable to low-power system-on-chip designs. Techniques related to a system's processing elements, volatile main memory and caches, non-volatile memory and on-chip interconnects are examined. Threat models for each subsystem and technique are considered. Performance overheads and other trade-offs for each technique are discussed. Defenses with similar threat models are compared.