Beyond real number modeling: Comparison of analog modeling approaches

In the last few years, several approaches were presented to model analog behavior using digital description languages. It was shown that these easily outperform, for abstract behaviour models, the classic SPICE simulation approaches and can run on digital, event-based simulators. But which is really the most efficient of these? Thus, this work aims to compare the most common “digital” approaches. At first, it focus on generating models based on directed real-type signals only - the so called real number models (RNM). Using a classic filter example, it presents one model in SystemVerilog and one model in SystemC. For both setups the simulation performance is evaluated. Next, to generalize and simplify the modeling process, alternative solutions are implemented. The System Verilog model is refined by a novel proposal, defining linear elements and a resolved, bidirectional signal type called EEnet. In contrast, a model is implemented in SystemC-AMS using standard elements based on electrical linear networks. The execution time of these models is measured as well. All results, generated on the very same hardware and operating system, are collected and presented in a single diagram for comparison. Although SystemC and SystemC-AMS models can outperform their related implementations in SystemVerilog in several aspects, this work points out some potential room for improvement. The results also allow to state some general rules for modeling and simulation.