A 64M CMOS Image Sensor using 0.7um pixel with high FWC and switchable conversion gain

This paper presents a 64 mega-pixel, backside-illuminated, CMOS image sensor using a 0.7um pixel pitch with a 7.0ke- linear full well capacity (FWC). A switchable conversion gain design was also demonstrated to have a high 18.0ke- FWC in 4-Cell pixel binning mode. Several new processes were implemented to overcome pixel performance degradation due to pixel scaling. As a result, this high FWC image sensor achieves low dark noise of 1.26e- and high quantum efficiency, comparable to larger pixel pitch products, such as 0.8um.