Dimensioning heterogeneous MPSoCs via parallelism analysis

In embedded computing we face a continuously growing algorithm complexity combined with a constantly rising number of applications running on a single system. Multi-core systems are becoming popular to cope with these requirements. Growing computational complexity is handled by increasing the number of cores and core types within one system - leading to heterogeneous many-core MPSoCs in the near future. One key challenge in designing such systems is to determine the number of cores required to meet performance, power and area constraints. In this paper we present a methodology that helps dimensioning these systems via a novel parallelism analysis methodology within seconds. The presented methodology has an average performance estimation error of less than 4% compared to transaction level simulation.