Lifetime Reliability Improvement of Nano-Scale Digital Circuits Using Dual Threshold Voltage Assignment

In nano-scale CMOS technology, circuit reliability is a growing concern for complicated digital circuits due to manufacturing process variation and aging effects. In this paper, a statistical circuit optimization framework is presented to analyze and improve the lifetime reliability of digital circuits in the presence of process variation and aging degradation. The proposed framework takes advantage of a process variation- and aging-aware gate-level delay degradation model to characterize and evaluate the lifetime reliability of combinational circuits. A metric called Guardband-Aware Reliability (abbreviated as GAR) is proposed for a fair evaluation of the lifetime reliability of combinational circuits considering a guardband and timing yield specified by the designer. Then, using a criticality metric, a set of statistically critical gates is selected for being optimized in the optimization framework. As the improvement procedure, the dual-threshold voltage assignment technique is applied to the identified critical gates to enable the manufactured chip to improve the lifetime reliability in terms of low timing yield loss. Experimental results on ISCAS'85 and ISCAS'89 benchmark circuits show that our proposed framework increases the circuit reliability up to 9.93% for a 6-year lifetime imposing less than 6.9% timing yield loss.