Optimal Layout of CMOS Functional Arrays

197920 citationsJournal Article

Authors

Abstract

This paper discusses the implementation of a random logic function on an array of CMOS transistors. A graph-theoretical algorithm which minimizes the size of an array is presented.

Topics & Keywords

Evolutionary Algorithms and Applications Cellular Automata and Applications VLSI and FPGA Design Techniques

UN Sustainable Development Goals

Affordable and clean energy

Publication Details

DOI: 10.1109/dac.1979.1600120

Field-Weighted Citation Impact: 2.64