Enabling Hybrid Bonding on Intel Process

In this paper, we holistically discuss the recent design, wafer fabrication and die assembly changes needed to enable hybrid bonding interconnect (HBI) on Intel process. HBI enables orders of magnitude improved interconnect density compared to solder which opens the doors to many new 3D packaging architectures. Starting with the design aspect, we show the physical interconnect changes that results in much lower parasitics. We also show the impacts on the top metal layer passives and power delivery and how to minimize these impacts through specific design changes. Afterwards, the wafer fabrication process changes are shown such as the fabrication of the bonding metal layers without causing excessive wafer warpage and the optimization of the chemical mechanical polishing process to enable smooth and flat surface dielectric and controlled-recess bonding pads. The assembly process changes are also summarized with special emphasis on the need for extremely clean die surface, high accuracy die placement and maximized test coverage. Finally, we show the design, fabrication, assembly and test results of active and passive test chips utilizing Intel advanced node process.